The present invention relates to a transmission amplifier control circuit for a mobile communication transmitter and more particularly to a circuit for controllably switching plural transmission power amplifiers according to transmission power. The present invention also relates to a method for controlling transmission amplifiers.
Recently, demands for mobile communication have caused a shortage of the number of channels. The CDMA (Code Division Multiple Access) system that provides a high frequency use efficiency has been come to attention for the mobile communication. The CDMA system requires an accurate, wide-range transmission power output control.
The spread spectrum system such as CDMA has the problem of distance which occurs in a difference in distance between a base station and each of terminals linked with the base station by radio and a difference between radio propagation paths. The base station, for example, receives a weak signal from a remote terminal and a strong signal from a nearby terminal. Hence, in the CDMA system in which all users utilize the same frequency, the receive signal from a remote terminal interferes with the strong signal from a nearby terminal. This is called the distance problem. To avoid this phenomenon, a good approach is that the base station equalizes receive power levels from respective terminals linked by radio. This requires that as the terminal moves, its transmission power is dynamically and accurately controlled. Various countermeasures have been proposed to vary the transmission output power.
One of methods of that type for obtaining a variable gain is a method for selectively using plural amplifiers. FIG. 5 is a block diagram illustrating the configuration of a prior art multistage amplifier. This configuration is disclosed by FIG. 3 in JP-A-212013/1985 (hereinafter referred to as Publication 1). The prior art method of selectively using plural amplifiers will be described below with reference to FIG. 5.
The multistage amplifier 5 shown in FIG. 5 consists of amplifiers 501 to 505, 507 to 511, and 513 to 517, selectors 506, 512, and 518, a detector 519, and a selection and decision circuit 521. In this configuration, the amplifiers 501 to 505 at the first stage each which has a different gain receives an input signal via the input terminal 1. The outputs of the amplifiers 501 to 505 are connected to the selector 506. The selector 506 selectively connects any one of the amplifiers 501 to 505 to the amplifiers 507 to 511 at the next stage. In such an operation, plural amplifier groups are connected in cascade mode. The outputs of the amplifiers 513 to 517 at the final stage are connected to the selectors 518 acting as a switch. The selection and decision circuit 521 decides an increase or decrease in gain according to a comparison result between a detection output detected by the detector 519 and a threshold input from the input terminal 520 and then selects a specific amplifier in each of the amplifier groups. This operation realizes the gain control of the entire system.
FIG. 6 is a block diagram illustrating the principle of a prior art power changeover amplifier which is disclosed in FIG. 1 of JP-A-156431/1988 (hereinafter referred to as publication 2). The power changeover amplifier of FIG. 6 aims at realizing the method of selecting an amplifier to suppress power consumption at a transmission time or the method of selecting an amplifier without adversely affecting a signal to be transmitted at a power switching time. The switching control method in a prior art power changeover amplifier will be described below by referring to FIG. 6.
The power changeover amplifier shown in FIG. 6 consists of a front-stage switching section 601, an amplifier 602, a variable phase shifter 603, an in-phase synthesis control section 604, a detection section 605, and a rear-stage switching section 606. In this arrangement, the bypass section (including the front-stage switching section 601, the variable phase shifter 603, and the rear-stage switching section 606) has the variable phase shifter 603 controlled by the in-phase synthesis control section 604 and is connected in parallel to the amplifier 602 to execute a power switching operation.
In this configuration, the front-stage amplifier 601 receives an input signal via the input terminal 1 at the time of a normal power outputting operation and then outputs an output signal to the output terminal 7 via the amplifier 602 and the rear-stage switching section 606. An input signal is input via the input terminal 1 at the time of a low power outputting operation. The front-stage amplifier 601 leads the input signal to the bypass section. Then the bypass section outputs an output signal to the output terminal 7 via the rear-stage switching section 606. At the transition from a normal power outputting time to a low power outputting time or from a low power outputting time to a normal power outputting time, the output power at the low power outputting time is temporarily mixed with the output power at the output of the normal power outputting time at the output of the rear-stage switching section 606. Problems do not occur when the mixing is mutually performed in phase. However, a mutual phase shift actually is unavoidable at a power mixing time. To avoid such a problem, the detection section 604 detects a phase shift. The phase synthesis control section 604 controls the variable phase shifter 603 according to the detected phase shift to set the phase shift to zero. In this operation, the switching operation can be simultaneously performed from the normal power outputting time to the low power outputting time or from the low power outputting time to the normal power outputting time with no occurrence of a phase shift.
A first problem is that the power changeover amplifier as illustrated in FIG. 6 has no timing control means for switching amplifier means because a phase shift (sometimes called phase rotation) occurs due to a momentary break of a transmission signal or selection of amplifier means when the amplifier means is changed during continuous signal transmission, so that the receiver cannot modulate the transmission signal and an error occurs in receive data. Particularly, in the transmitter and receiver employing the phase modulation according to the synchronous detection scheme, since information is allocated to a phase, an error occurs in receive data when the phase of the transmission data shifts with respect to the pilot signal being the reference of the transmission data.
The second problem is that in the prior art combination of amplifiers connected in a multistage state shown in FIG. 5, the selection and decision circuit selects an amplifier using a signal detected by the detector that detects the output power from the multistage amplifier. That arrangement is effective to saturation of the output power. However, since the gain of the entire system is decided by a combination of fixed gain values, an increased number of amplification stages are required for a fine gain adjustment.
The third problem is that the prior art power changeover amplifier shown in FIG. 6 is not suitable to vary the gain over a wide range. This system is effective to handle signals serially chained because the amplifier can be selected under the in-phase synthesis control, with the phase continued. However, the switching operation must be made in two levels including a normal power outputting operation and a low power suppressing operation by bypassing.
FIG. 6 does not show the power changeover amplifier including a great number of amplifiers connected. The power changeover amplifier corresponds to deal with a specific fading. Hence, where amplifiers each of which has a different gain are connected in a multistage mode to execute a wide gain control, it is needed to control a great number of amplifiers each to which a variable phase shifter is added. Such an arrangement has the problem of resulting in a large circuit scale and complicated control to each amplifier. Such a configuration is not suitable to a mobile communication such as a portable digital mobile communication terminal which must be configured in a compact size.